HoLiSTEP hits 500 nm holographic lithography milestone

The HoLiSTEP project says it has demonstrated 500 nm patterning and single-exposure processing on high-topography wafers using sub-wavelength holographic lithography. The results point to a lower-cost route for sub-micron manufacturing on complex substrates in MEMS, photonics, advanced packaging and sensors.

Why it matters: - HoLiSTEP’s results target a hard problem in semiconductor manufacturing: patterning on non-flat, multi-level substrates without adding process complexity. - The approach could matter for MEMS, integrated photonics, advanced packaging, sensors and micro-optics, where surface variation and focus control can limit pattern quality. - Holographic lithography could also reduce mask complexity by shifting image correction and resolution enhancement into the mask synthesis stage.

What happened: - HoLiSTEP demonstrated 500 nm patterning on flat silicon wafers using its 388 nm test-bench platform. - The project also showed two-level image generation across surfaces separated by 100 µm in a single exposure. - A separate experiment exposed spray-coated resist on structured silicon wafers with 100 µm-deep etched cavities in one holographic step. - The structured wafers test showed comparable pattern quality on both the top wafer surface and the cavity surface.

The details: - Sub-Wavelength Holographic Lithography (SWHL) uses holographic masks to reconstruct the target image at the wafer plane. - The method is being developed as a cost-effective alternative to conventional projection photolithography. - Unlike standard lithography optimized for planar wafer surfaces, holographic lithography can tailor optical fields for 2D and 3D high-resolution patterning in a single exposure. - The 500 nm result was transferred from holographically generated aerial images into photoresist. - The 100 µm-separated image demonstration points to applications on stepped surfaces, sidewall slopes and vertically separated device layers. - HoLiSTEP says the work shows structured wafers with deep cavities can be exposed in a single holographic step. - The project says holographic masks can be built from relatively simple elements, with correction and resolution enhancement handled during synthesis.

Between the lines: - The main value is not just the 500 nm feature size. It is the combination of sub-micron resolution and flexibility on difficult substrates. - That combination could matter more as device designs move toward more 3D integration and more complex wafer topography. - The test-bench results also suggest a potential manufacturing path that avoids some of the cost and process burden of conventional single-plane exposure methods.

What’s next: - HoLiSTEP plans to move from the validated 388 nm test bench toward a 345 nm industrial platform. - The project says that step would bring the system closer to the wavelength, resolution and architecture needed for future industrial deployment. - HoLiSTEP is seeking industry discussions with companies in MEMS, photonics, advanced packaging, sensors, micro-optics, semiconductor equipment, materials and high-value microfabrication. - The project aims to use those conversations to define use cases, process requirements, substrate formats and performance targets.

The bottom line: - HoLiSTEP’s milestone is a proof point for holographic lithography as a possible industrial alternative for high-resolution patterning on complex surfaces. - The next hurdle is turning the 388 nm demonstration into a 345 nm platform that can support real manufacturing needs.